library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity pwm_generator_tb is
end pwm_generator_tb;

architecture test_bench of pwm_generator_tb is
  
  constant CLK_PERIOD : TIME := 20 ns;
  
  signal clk : std_logic;
  signal reset_n : std_logic;
  signal pwm_in : std_logic_vector(7 downto 0);
  signal pwm_out : std_logic;
  
  component pwm_generator is
  port(
		clk, reset_n  : in std_logic;
		pwm_in : in std_logic_vector(7 downto 0);
		pwm_out : out std_logic
	  );
  end component;
  
begin
  
  DUT : pwm_generator port map (clk     => clk,
                                reset_n => reset_n,
                                pwm_in  => pwm_in,
                                pwm_out => pwm_out);
                                
  clk_gen : process
  begin
    clk <= '0';
    wait for CLK_PERIOD/2;
    clk <= '1';
    wait for CLK_PERIOD/2;
  end process;
  
  stimulus : process
  begin
    reset_n <= '0';
    pwm_in <= std_logic_vector(to_unsigned(50, pwm_in'length));
    wait for 4*CLK_PERIOD;
    reset_n <= '1';
    wait for 1000*CLK_PERIOD;
    pwm_in <= std_logic_vector(to_unsigned(200, pwm_in'length));
    wait for 1000*CLK_PERIOD;
    wait;
  end process;
  
end test_bench;